One of the critical challenges for circuit designers is managing timing of their designs. Precise control over timing and clock signals can enable higher performance and more reliable designs. This challenge to manage timing, however, has become greater as circuits grow more complex and clock frequencies increase.
Dual or double data rate (DDR) applications and designs have become increasingly popular as clock rates continue to increase into the gigahertz range and beyond. At very high frequencies, distributing an accurate, jitter-free clock becomes increasingly difficult. A double data rate application mitigates this problem by using both rising and falling edges of a clock. Thus, a DDR application only requires a clock having half the frequency of the corresponding data rate. DDR interfaces are commonly used for memory interfaces, as well as many other applications.
Conventional DDR techniques typically use 2 or more conventional flip-flops to obtain the desired functionality. For instance, a simple DDR input may include two standard edge-triggered flip-flops. One flip-flop may be configured to latch data on rising edge and the other may be configured to latch data on falling edges. In some instances, an inverted clock may be provided to a rising edge-triggered flip-flop to provide falling edge functionality. The DDR data stream would then be provided to the input of both latches.
Conventional DDR circuits, however, may have certain disadvantages. As noted above, a conventional DDR interface includes at least two separate flip-flops, thereby occupying greater area than single data rate (SDR) interfaces, which may only have one flip-flop. Furthermore, conventional DDR circuits may not be capable of operating at the high speeds required by many modern applications. Also, a conventional DDR circuit can introduce asymmetry or other errors in a design.
Accordingly, there is a need for a dual-edge sampler that addresses these and other shortcomings of conventional DDR circuits.